1、This is a challenging job role to decide timing signoff criteria for high performance ASIC/CPU in advanced technology node(14nm/7nm).
2、Work with various teams across foundry PDK/technology, STA, CAD, circuit design to analyze various physical effects such as PVT variations, aging, crosstalk noise etc. in advanced technology nodes on device/wire delay. Work include extensive spice simulation, data analysis, corner reduction, sensitivity factor analysis, STA timing tool correlation with spice delay measurement, etc. The end result is the timing signoff recipe, signoff corners, timing margin for high performance ASIC/CPU.
3、Drive adoption and deployment of advanced timing signoff methodology.

1、MSEE with 15+ years(or PhD with 12 years) of experience with solid academy background/knowledge in device/technology, circuit design/analysis, timing signoff, STA and STA tool behavior, RC extraction, physical design and CAD/Methodology.
2、Familiar with and deep understanding of the behavior of PrimeTime, Tempus, StarRCXT, fineSim, Hspice is a must!
3、Good programming skills in Perl/Python/Tcl.
4、Working experience with and solid understanding of POCV, timing signoff in advance technology nodes.
5、Working experience with AVS/DVFS/AVFS in timing signoff or post silicon bring up/performance yield analysis is a big plus.
6、Good team player, please!